2.3 Selecting Semiconductor Devices for
the Design (Q1, Q2, D8, D9, D10, D11)

Before selecting electrical components
for output diodes and FETs a power budget needs to be

set for each component, PSEMI, to ensure that the
efficiency goal (ç) of 85% can be achieved. To

achieve this design goal a power budget
was set for each semiconductor device to dissipate

less than one sixth the maximum
allowable losses, which for this design was roughly 5 W.

PSEMI _ POUT(max)_1__

6 _ _ 5 W

SLUA312 ? May 2004

4 200-W Interleaved Forward Converter
Design Review Using TI’s UCC28221 PWM Controller

2.4 Forward FET Selection (Q1 and Q2)

Finding the proper FETs for the design
to achieve the efficiency goal is always a trial and error

process. The following equations will
help you estimate the maximum drain to source voltage of

the FET (VDS(max)) and the power
dissipated by the FET. IPEAK(Q1) is the peak FET current.

PSWITCH is estimated transitional losses of the FET,
where ton and toff are the rise and fall times

of the FET. PGATE is the losses
generated by driving the gate of the FET. PCOSS is the FET

capacitance (COSS) losses. The sum of
all of these losses (PQ1) gives a good estimation of total

FET losses. For this design we selected
a Vishay FET part number SUM65N20?30, which is a

200-V FET that had an estimated loss
off roughly 6.8 W, this loss was slightly higher than what

was budgeted and left a little less
room for the losses of the output rectifiers.

VDS(max) _    VIN(max)